This invention relates generally to devices and methods of forming electrical connections for integrated circuits and more specifically relates to devices and methods of fabricating thin-film multilayer, interconnect signal planes for connecting semiconductor integrated circuits.
In order to fully take advantage of the performance of VLSI devices that will become available in the near future, the packaging of the chips in a computer system becomes a very important issue. The package must be capable of (i) handling a large number of signal lines, (ii) minimizing the distortion and delay of pulses propagating between chips, and (iii) enhancing its capability to dissipate an increasing amount of heat generated by the VLSI chips.
Very sophisticated, high-density multilayer circuit boards (MLB) are available which currently meet the requirements of presently available integrated circuit devices. However, a significant extension of the present packaging technology or the development of a new technology is expected to be needed to satisfy future requirements for the next generation of both mainframe and super minicomputers that will appear in the market in the next two to four years. Furthermore, increasing sophistication in military electronics demands similar advances in packaging in that application.
The advantage of applying thin-film technology to fabricate high-performance packages for semiconductor devices was recognized by researchers at Raytheon Corporation. This research is described in Lewis, "High-Density High-Impedance Hybrid Circuit Technology for Gigahertz Logic" IEEE Transactions on Components, Hybrids, And Manufacturing Technology, CHMT-2, No. 4 (Dec. 1979) 441-450. The conclusion of their work is that if the thickness of the natural conductor is over 1.7 microns, the yield of making such a thin-film package is essentially zero. They trace the difficulty to a well-known problem in semiconductor fabrication known as step coverage. The most obvious difficulty can be easily seen from FIG. 1. In depositing several microns of second-level metal over the first level, one immediately faces a very severe problem in step coverage. In the region where a second-level conductor crosses the edge of a first-level conductor 12, the metal line will be much thinner, leading to possible line breakage. Furthermore, if the dielectric layer is not thick enough, there is also a possibility that conductors in adjacent layers may be shorted. On the other hand, producing an overly thick dielectric layer is time consuming, and will be harder to etch through for via hole formation.
In conventional semiconductor fabrication technology where the thickness of the interconnect metal conductor lines are approximately 1/2 to 1 micron thick, there have been attempts to planarize multilayer interconnects. This is generally described in Moriya et al., "A Planar Metallization Process--Its Appliction to Tri-Level Aluminum Interconnection," International Electron Devices Meeting 1983 IEEE (1983) 550-553. Because of the vast difference in thickness of the metal conductor lines that is associated with a multichip package as opposed to a conventional semiconductor device, the technology associated with planarization in conventional semiconductor devices cannot easily be extended to the problems associated with the fabrication of multichip packages.